Senior VHDL FPGA Engineer

Overview

In this role you will engineer embedded VHDL firmware for airborne electro-optics, contributing across the product lifecycle. You’ll work with leading FPGA/SoC devices and collaborate with cross-functional teams to shape future products. You’ll translate system requirements into firmware, drive design reviews, and support integration and verification in a safety-conscious environment. This opportunity combines hands-on FPGA work with system-level collaboration and a clear impact on mission-critical platforms.

Pay / Benefits

• Hybrid working
• Private healthcare
• Pension scheme
• Training: 4000+ courses via Coursera and LinkedIn Learning
• Flexible hours
• Further benefits listed on company site

Responsibilities

• Firmware requirements capture and management
• FPGA design and analysis
• Production of design documentation and evidence for design reviews
• Development of FPGA test and integration plans
• System integration work with PCB designers and embedded software engineers
• Support firmware designs through the company firmware process (training provided)
• Modification of existing firmware designs and test benches

Key requirements

• Experience with FPGA technologies (Xilinx, Microsemi/Actel, or Lattice) and their tools
• Advanced verification techniques using VHDL or SystemVerilog/UVM
• Ability to specify complex timing and area constraints for FPGA place-and-route
• Deriving detailed firmware requirements from system-level requirements
• Structured firmware lifecycle experience (DO-254 or similar)
• Experience with safety-related firmware (IEC 61508 advantageous)
• Debugging firmware and supporting hardware/system-level verification and integration
• Strong cross-disciplinary communication skills
• Familiarity with Siemens EDA tools (HDL Designer, ModelSim/Questa) is a plus

• Effective communication across disciplines
• Methodical, structured problem-solving
• Mentoring capabilities (nice to have)
• FPGA design and verification
• VHDL / SystemVerilog / UVM
• Timing and area constraint specification

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