Senoir FPGA Engineer – Quant Marketmaking

Overview

In this role you will design latency-optimised FPGA systems and high-speed modules to support trading, research, and networking pipelines. You’ll work in a small senior team building a greenfield FPGA capability and collaborate with ASIC, software, and infra groups to co-design tightly integrated platforms. You’ll leverage RTL expertise and hardware-tuned development to push performance and throughput. This opportunity offers ownership across the full lifecycle and the chance to shape infrastructure from concept to deployment.

Responsibilities

• Design latency-optimised FPGA architectures using Verilog/SystemVerilog
• Develop high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining
• Validate designs with simulation and formal tools (Verilator, Cocotb)
• Collaborate across ASIC, software, and infra teams for co-design
• Contribute to tooling, flow improvements, and potentially DSL extensions

Key requirements

• Strong RTL skills with experience building optimized designs
• Programming skills in C, C++ or similar
• Solid grasp of timing closure, datapath design, and hardware-level performance tuning
• Familiar with toolchains (Vivado, Quartus) and debugging workflows
• Comfortable owning the full development cycle and working close to hardware
• Interest in improving hardware workflows or applying high-level techniques

• Cross-functional collaboration
• Ownership and end-to-end accountability
• Ambition to improve hardware workflows
• Verilog/SystemVerilog
• PCIe, Ethernet, DDR/QDR interfaces
• Timing closure

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