Principal Design Engineer

Overview

In this role you design and integrate RTL for complex subsystems within SoCs, collaborating with global teams to optimize performance and power. You translate subsystem architectures into microarchitecture specifications and RTL, support verification and debugging, and work with performance and power teams to improve KPI outcomes. Your contributions help refine IP interworking and design methodologies across projects. This position offers the chance to influence multi-IP integration, contribute to state-of-the-art processing systems, and thrive in a hybrid work environment with a strong emphasis on collaboration.

Pay / Benefits

• relocation package with visa sponsorship
• accommodations during recruitment
• hybrid working arrangement
• equal opportunities employer

Responsibilities

• analyze incoming IPs, their interfaces, and how they interwork with subsystem/SoC components
• develop subsystem microarchitecture specifications and RTL
• review verification test plans and assist with debugging
• collaborate with performance and power teams to evaluate and improve KPIs
• perform design checks, fix bugs, and propose refinements to IP teams
• identify improvement opportunities and enhance team design methodologies
• guide and support team members and coordinate with Project Management on plans and schedules

Key requirements

• Bachelor or Master in Electrical/Computer Engineering or equivalent
• digital hardware design experience and Verilog HDL
• understanding of complex SoC development methods and techniques
• experience with static design checks (CDC, RDC, X-prop, Lint, UPF)
• ability to create design specifications and work with Verilog/SystemVerilog and verification methodologies
• proven delivery of sophisticated RTL subsystems within deadlines
• ability to perform high-level PPA trade-offs and drive ownership
• experience with synthesis, timing analysis, and power management
• strong communication and collaboration skills

• hard-working
• creative
• motivated
• ARM-based designs and architectures
• AMBA protocols (ACE-Lite, AXI, AHB, APB, CHI)
• processor subsystems, interconnects, security subsystems, PCIe subsystems, system power management

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