Physical Design Engineer

Overview

In this role you will contribute to the full chip development lifecycle within a collaborative Cambridge team. You will drive physical design work from netlist to silicon delivery, helping to shape high-volume computing/embedded products. You’ll tackle challenges in ASIC/SoC implementation, enabling timely product release and robust performance. This position offers broad exposure in a close-knit environment where your contributions directly impact product success. Join a culture that values technical excellence and real-world impact.

Responsibilities

• Oversee the complete physical implementation flow from netlist to GDSII
• Perform floorplanning, power planning, placement and optimization, clock tree synthesis, routing and physical verification closure
• Lead timing closure and static timing analysis
• Conduct logic synthesis, equivalence checking and place-and-route methodologies
• Work on complex ASIC or SoC designs within advanced semiconductor environments

Key requirements

• At least two years of industry experience in Physical Design or Physical Implementation
• Strong understanding of modern ASIC implementation flows and methodologies
• Solid communication skills with cross-functional teams

• Strong communication
• Cross-functional collaboration
• Team contribution
• Physical implementation flow (netlist to GDSII)
• Floorplanning and power planning
• Placement, optimization, clock tree synthesis

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