Senior Staff RTL Design Engineer – CPU Frontend

Overview

As a CPU Microarchitecture/RTL design engineer at SiFive, you will help design industry-leading CPU cores based on open-source RISC-V. You’ll work across design, verification, and implementation to deliver high-performance hardware IP. The role emphasizes rapid delivery, collaboration, and documentation within a fast-paced environment. You will shape core features, ISA extensions, and optimization efforts that drive scalable silicon solutions.

Pay / Benefits

• comprehensive benefits package
• healthcare
• retirement plans
• paid time off
• competitive pay
• equity eligibility

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel
• Integrate design content into Chisel/FIRRTL framework and contribute improvements for automatic configuration and testing
• Perform initial sandbox verification and develop thorough verification test plans with the design verification team
• Collaborate with the physical implementation team to optimize design for frequency, area, and power
• Cooperate with performance modeling for exploration and optimization to meet performance goals
• Document knowledge and contribute to a culture of collaborative design

Key requirements

• BS/MS in computer science, computer engineering, electrical engineering or related field, or equivalent experience
• 7+ years of design experience
• Experience with CPU RTL design in instruction fetch/decode, branch prediction, coherent caches, cache prefetching, TLBs
• Proficiency in Verilog, SystemVerilog, or VHDL
• Strong software engineering background including functional programming and DSLs
• Experience with compiler infrastructures or DSLs and data modeling for intermediate representations
• Experience with test-driven development and adaptive unit tests
• Attention to detail and teamwork orientation

• attention to detail
• teamwork
• self-motivation
• Verilog
• SystemVerilog
• VHDL

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