Design Verification Engineer

Overview

As a Verification Engineer in a world-class silicon team, you drive verification across CPU/ASIC environments to ensure robust, scalable designs. You collaborate across sites, translate requirements into test plans, and provide feedback to architects. You will contribute to shared verification infrastructure and help diagnose complex issues, shaping the verification strategy for cutting-edge AI compute hardware. This role offers scope to influence product quality in a high-growth AI-focused company.

Pay / Benefits

• flexible working
• generous annual leave
• private medical insurance and health cash plan
• dental plan
• pension (matched up to 5%)
• life assurance and income protection

Responsibilities

• Verification activities within the verification team
• Facilitate communication between sites
• Verification planning, specification and closure of functional coverage
• Provide feedback to architects
• Test generation and failure diagnosis/triage
• Contribute to shared verification infrastructure

Key requirements

• Verification experience in relevant industry
• Proven leadership and planning skills
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• SystemVerilog, Python, C++, Linux
• UVM
• SVA
• LLVM, GCC
• SGE or other DRMS
• XML and XPath/XSLT

• Cross-functional collaboration
• Problem solving
• Effective communication
• SystemVerilog
• Python
• C++

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