Staff RTL Design Engineer – CPU Midcore

Overview

In this role you will design and evolve high-performance RISC-V CPU cores, contributing to SiFive’s open-source hardware IP. You’ll work across design, verification, and physical implementation to deliver optimized cores and ISA extensions. You’ll collaborate with multiple teams to push performance, area, and power goals, while documenting work for the broader engineering community. This position offers hands-on influence on next-gen CPU architectures in a fast-paced, collaborative environment.

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel
• Integrate design content into Chisel/FIRRTL framework and contribute to framework improvements for automatic configuration and documentation/testing
• Perform initial sandbox verification and create/execute verification test plans with the design verification team
• Collaborate with the physical implementation team to meet frequency, area, and power targets
• Work with the performance modeling team for performance exploration and optimization
• Microarchitecture development and specification with emphasis on knowledge sharing and documentation

Key requirements

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience
• 5+ years of design experience
• Academic or professional experience with CPU RTL design
• Proficiency in hardware RTL design with Verilog, SystemVerilog, or VHDL
• Strong software engineering background with object-oriented, functional programming, and DSL/metaprogramming skills
• Experience with compiler infrastructures and data modeling for intermediate representations
• Test-driven development and ability to write adaptive unit tests
• Attention to detail and team-oriented mindset

• teamwork
• attention to detail
• communication
• Verilog/SystemVerilog/VHDL
• Chisel/Scala (nice-to-have)
• Bluespec (nice-to-have)

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