Principal Design Engineer – High-Speed Interconnect

Overview

As an RTL/ microarchitecture specialist at Arm, you own the microarchitecture, RTL, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink) across silicon products. You translate requirements into executable architectures, interfaces, and synthesizable RTL, leading the development cycle from concept to delivery. You collaborate with multiple teams to meet performance, power, and timing targets while mentoring engineers. This role offers impactful work shaping next-generation interconnects in a collaborative, inclusive environment.

Pay / Benefits

• hybrid working
• flexible working
• accommodations during recruitment
• inclusive environment
• collaborative culture
• office-based planning days

Responsibilities

• Own microarchitecture, RTL development, and integration of PCIe, CXL, and UALink subsystems across multiple silicon products
• Translate system and protocol requirements into specifications, interfaces, registers, and RTL
• Drive end-to-end development from concept through RTL, integration, verification support, and delivery
• Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet targets
• Analyze traffic, workloads, queue depths, credits, and buffer requirements to guide implementation tradeoffs
• Lead technical reviews, debug cross-functional issues, improve methodologies, and mentor engineers

Key requirements

• 8+ years in RTL build, microarchitecture, or related semiconductor roles
• Deep hands-on expertise in SystemVerilog and high-performance digital subsystems
• Strong understanding of PCIe, CXL, and UALink (transaction flows, flow control, retries, error handling, host/device integration)
• Experience with coherent/non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems
• Solid knowledge of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, backpressure
• Experience with CDC, RDC, reset sequencing, low-power build, lint, X-propagation, formal verification, synthesis, timing analysis, waveform debugging
• Ability to translate architectural requirements into clear microarchitecture documents and high-quality RTL
• Proven technical leadership, communication, and delivery across multi-functional teams
• Bachelor’s degree, or equivalent in Electrical/Computer Engineering, Computer Science, or related field

• leadership
• communication
• team collaboration
• SystemVerilog
• RTL development
• PCIe

…