Staff Digital IC Design Engineer

Overview

In this role, you will design and integrate digital blocks for mixed-signal ASICs from definition to production, collaborating with Product Definition, IC Design and Test teams. You will implement RTL in SystemVerilog, create simulation and test benches, and drive DFT and P&R activities to ensure robust, production-ready designs. You’ll lead a small team, advance digital design methodology, and contribute to architecture and FPGA emulation studies. This is a hands-on, impact-focused position at the Cambridge site with cross-centre collaboration.

Pay / Benefits

• Health & wellbeing
• Private healthcare
• Enhanced sick pay
• Group income protection
• Employee assistance programme
• Group life scheme`,`Cycle2Work – savings on bike purchases

Responsibilities

• Develop functional digital blocks and contribute to mixed-signal ASICs from definition to production maturity
• Support Product Definition with feasibility, architecture, and digital blocks for FPGA emulation
• Complete RTL design in SystemVerilog to meet system requirements
• Create block-level test benches for digital blocks verification
• Create behavioural models and top-level test benches for system-level verification and regression
• Complete digital synthesis with physical constraints to meet PPA requirements
• Define and implement DFT architecture; perform scan insertion and ATPG for test coverage
• Oversee digital place-and-route and ensure post-layout timing closure
• Generate design documentation and participate in design reviews
• Lead and oversee team members to achieve objectives
• Lead digital design methodology improvements within the company

Key requirements

• MSc/MEng or PhD in Electronics Engineering or related subject
• Minimum 5 years’ experience in digital IC design using standard cell libraries
• Expertise in SystemVerilog and fully synthesised digital design flow with RTL and logic synthesis
• Familiarity with constraints and automatic place-and-route flow for physical design
• Experience with production test and methods to maximise digital test coverage (e.g., scan)
• Experience in digital power optimisation
• Lab debugging of digital functions with suitable test equipment
• Experience with scripting languages such as TCL/Python
• Experience producing accurate and complete documentation

• leadership and mentoring
• cross-functional collaboration
• problem-solving orientation
• SystemVerilog
• RTL design
• logic synthesis

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