Senior FPGA Engineer – Xilinx Artix-7 & VHDL Expert

HUBER+SUHNER Polatis is seeking an experienced FPGA engineer to design and verify VHDL-based logic for Artix-7 FPGAs using Vivado. You will develop deterministic FSMs, implement and validate low-level interfaces (I2C, SPI, UART), and drive tests from board bring-up to production readiness.

The role emphasizes hardware verification, timing closure, documentation, and cross-functional collaboration with electronics and software teams.

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