Senior DDR Validation Engineer | MRL Consulting

Overview

As a Senior DDR Validation Engineer, you will validate DDR3/DDR4 interfaces and drive system bring-up for advanced modem platforms and satellite systems. You will design and execute validation plans, analyze margins across timing, voltage, frequency, and temperature, and debug memory training issues. You’ll support FPGA bring-up and hardware/software co-validation while ensuring robust high-speed interfaces. This role offers hands-on impact in a cutting-edge engineering environment, working with multidisciplinary teams to deliver production-ready solutions. You will shape validation processes and contribute to next-generation communications technology.

Responsibilities

• Validate DDR3/DDR4 interfaces and perform system bring-up
• Develop and execute DDR validation plans including margin analysis
• Debug memory training, calibration and initialization issues
• Support FPGA bring-up and hardware/software co-validation
• Validate high-speed interfaces (DDR, PCIe, USB)
• Perform signal integrity analysis and automate tests (Python, C/C++)
• Collaborate with cross-functional teams to deliver robust solutions

Key requirements

• 5+ years’ experience in DDR validation, FPGA development or high-speed digital systems
• Strong knowledge of DDR3/DDR4, JEDEC standards and memory controller architecture
• Experience with FPGA bring-up, Python, C/C++, Git and automated regression frameworks
• Hands-on experience with oscilloscopes and JTAG debuggers
• Degree in Electrical Engineering, Computer Engineering or related discipline
• Excellent analytical, debugging and communication skills

• analytical thinking
• strong communication
• team collaboration
• DDR3/DDR4
• JEDEC standards
• memory controller architecture

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