Senior Digital ASIC Design Engineer

Overview

As a Senior Digital ASIC Design Engineer, you will own the front-end digital development of our ASICs, spanning architecture, RTL, verification and silicon bring-up. You’ll work closely with analogue and system engineers to define interfaces and calibration, and guide designs through lint, timing and synthesis. This is a hands-on, ownership-driven role across the full front-end flow, including FPGA prototyping and pre-silicon validation. You’ll shape low-power, high-integration digital solutions for medical and neurotechnology applications, enabling reliable, scalable silicon.

Responsibilities

• Own architecture and RTL development of digital control, communication and power management functionality
• Develop clean, synthesizable Verilog/SystemVerilog for low power mixed signal ASICs
• Build and maintain SystemVerilog verification environments with assertions, coverage and self-checking testbenches
• Collaborate with analogue and system engineers to define interfaces, registers, clocks and calibration
• Lead lint, CDC/RDC, synthesis and timing analysis, in coordination with Physical Design
• Support FPGA-based prototyping, pre-silicon validation and eventual silicon bring-up
• Contribute to design reviews, technical documentation and verification planning

Key requirements

• Strong commercial experience in digital ASIC design and RTL development
• Hands-on experience with Verilog and/or SystemVerilog
• Experience taking digital designs from specification/architecture through RTL development and synthesis
• Good understanding of digital verification, including testbenches, assertions and functional coverage
• Experience with front-end quality checks such as lint, CDC/RDC and timing constraints
• Experience working on mixed signal chips is highly desirable
• Willingness to own and navigate the full ASIC development flow

• technical ownership
• cross-functional collaboration
• proactive problem-solving
• Verilog
• SystemVerilog
• RTL development

…