Overview
As a Design Verification Engineer, you will contribute to digital verification for complete mixed-signal ICs, lead verification activities, and advance verification methodologies. You’ll join Edinburgh or Newbury teams, collaborating cross-functionally to ensure first-time-right silicon. You’ll work on complex testbenches and hands-on verification, shaping cutting-edge projects in a global, inclusive environment. This role combines technical rigor with leadership and opportunities for personal growth.
Pay / Benefits
- personal and professional development
- flat, inclusive culture
- hybrid remote work model
- global team exposure
- opportunity to work on cutting-edge projects
- competitive benefits
Responsibilities
- Define IC verification plan linking requirements to test cases
- Lead teams of verification engineers to deliver verified ICs
- Create reliable and reusable testbenches for complex subsystems and ICs
- Participate in verification specialist groups and contribute to methodology discussions
- Coach and support the verification team to follow and improve defined practices
- Hands-on project design/verification involvement
Key requirements
- Degree in Electronics/Computer Science or related discipline (BEng/BSc/MEng/MSc)
- Proven track record delivering first-time successful mixed-signal IC verification
- Metric-driven verification: planning, requirements extraction, constrained random verification, coverage analysis
- SystemVerilog and SystemVerilog Assertions (SVA)
- Testbench design with UVM/OVM/eVMM
- RTL, Testbench, OOP, gate-level (including SDF) debugging
- Strong problem-solving ability and innovative mindset
- Innovative
- Creative
- Lateral thinking
- SystemVerilog
- SVA
- UVM/OVM/eVMM
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