Staff Design Verification Engineer

Overview

In this role you will ensure functional correctness and robustness of complex digital and mixed-signal ASICs using advanced verification methodologies. You collaborate with architects, designers, and fellow verifiers to deliver high-quality silicon. You will create testbenches, write verification tests, and drive both block-level and full-chip verification, including regression and post-silicon validation. The position offers impact through process improvements and mentoring, within a mission-driven hardware team. You will work with cross-functional groups to shape robust verification strategies.

Pay / Benefits

• remote work option
• flexible and inclusive work environment
• Employee Resource Groups

Responsibilities

• Develop and execute verification plans for complex mixed-signal ASICs
• Create and maintain SystemVerilog/UVM testbenches
• Write and debug tests for functionality, performance, and corner cases
• Perform block-level and full-chip verification including simulation, coverage, and regression
• Collaborate with design engineers to define verification requirements
• Analyze and resolve verification and post-silicon issues
• Mentor junior engineers and improve verification processes
• Participate in code reviews and drive continuous improvement of verification practices
• Manage and debug gate-level simulation (pre/post-layout, with/without SDF timing)

Key requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years in digital and/or mixed-signal design verification
• Proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium)
• Strong understanding of RTL design and ASIC development flows
• Scripting skills (Python, Perl, Tcl) for automation
• Familiarity with formal, assertion-based, and coverage-driven verification
• Excellent problem-solving and attention to detail
• Strong communication and teamwork abilities
• Experience with version control and CI/CD workflows
• Experience with other verification methodologies (e/eRM, hardware/software co-simulation)
• Knowledge of standard protocols (AMBA, I2C)

• problem-solving
• communication
• teamwork
• SystemVerilog
• UVM
• Synopsys VCS

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