Staff Design Verification Engineer

Overview

In this role you will contribute to pre-silicon and post-silicon verification of impactful mixed-signal products, shaping verification methodologies for the team. You will bridge verification and validation environments across global groups, driving high coverage and robust design validation. The role sits in the Data Center and Energy team, aligning with ADI’s mission to advance intelligent edge solutions. You will work with cross-functional partners to tackle challenging AMS and DMS verification problems, leveraging a scalable, best-practice flow. This is an opportunity to impact next-generation analog/mixed-signal technology at scale.

Responsibilities

• Contribute to pre-silicon verification of mixed-signal products
• Bridge verification and validation environments for post-silicon support
• Aim for 100% verification coverage across DMS and AMS, at top-level and IP-level
• Establish and continuously improve verification flows, methodologies, and models

Key requirements

• Bachelor/Master’s degree in electronics engineering or equivalent with 7+ years of experience
• Contributions to full chip level verification of mixed signal devices
• IC top-level DMS SV/UVM verification, Object-Oriented and Randomized Verification, and Gate Level Simulation
• Top-level metric-driven AMS simulations
• Modeling and validation of analog blocks (RNM, Verilog-AMS)
• Proficiency with Cadence tool suite (Xcelium/IMC/Virtuoso)
• Verification planning tools (ePlanner/vManager) and scripting languages (Shell/TCL/Perl/Python)
• Understanding of FPGA prototyping/tools and scripting for pre-silicon validation
• Experience with multiple clock and power domains
• Strong verbal and written communication and global collaboration ability

• strong communication
• collaboration
• problem-solving
• AMS/DMS verification
• DMS SV/UVM
• Object-Oriented and Randomized Verification

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