Hardware Verification Engineer

Overview

In this role you will own verification across block, subsystem, and multi-FPGA designs within a fast-growing hardware team. You will partner with the Lead Verification Engineer to shape and execute the verification strategy in a cross-disciplinary, quantum-focused environment. You’ll develop scalable UVM-based testbenches and drive system-level verification with a clear focus on risk and coverage. This is a hands-on, impact-driven position that connects RTL, simulation, and hardware, with opportunities to mentor others and contribute to the verification roadmap.

Responsibilities

• Own verification strategy and execution for block-level, subsystem, and multi-FPGA systems
• Develop scalable UVM-based testbenches
• Drive verification with focus on risk, coverage, and system-level behavior
• Collaborate with Lead Verification Engineer to define verification approach
• Mentor junior verification engineers (where applicable)
• Work across RTL, simulation, and hardware to debug issues

Key requirements

• Strong hands-on SystemVerilog and UVM expertise
• Proven ability to debug across RTL, simulation, and hardware
• Experience in functional verification including planning and strategy ownership
• Exposure to programming languages such as C, C++, and Python
• Formal verification experience (plus)
• Experience mentoring junior verification engineers
• Ability to work effectively with ambiguity and changing requirements

• ability to work with ambiguity
• mentoring and coaching
• cross-functional collaboration
• SystemVerilog
• UVM
• debug across RTL, simulation, and hardware

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