Lead Full-Chip Physical Design Architect

Aion Silicon is seeking a Principal Physical Design Engineer to lead complete physical implementation of complex SoCs and ASICs. You will own RTL handoff to sign‑off and GDSII generation, coordinating with RTL, STA, DFT, packaging, foundry and EDA partners globally.

You will mentor engineers, drive design strategies for 7nm and below, and ensure timely tape‑outs while staying ahead with industry best practices.

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