Hybrid Design Verification Engineer (SystemVerilog/UVM)

Company: IC Resources
Apply for the Hybrid Design Verification Engineer (SystemVerilog/UVM)
Location: City of Edinburgh
Job Description:

IC Resources has an opportunity for Design Verification Engineers to join a leading UK semiconductor engineering team. You’ll work on ASIC/SoC verification lifecycles, owning the verification of complex digital subsystems and mixed-signal ICs.

Positions open at multiple levels from engineer to senior/principal, with hybrid work in Edinburgh or Newbury and a strong engineering culture.

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Posted: August 17th, 2026