Senior RTL Design Engineer — High-Performance RISC-V Core

SiFive is seeking a CPU Microarchitecture/RTL design engineer to join a team delivering industry-leading CPU cores based on RISC-V. You will design features, ISA extensions, and integrate content within SiFive’s Chisel/FIRRTL framework, enabling automatic configuration and validation.

The role emphasizes high-performance hardware IP, collaboration across verification, physical design, and performance teams, with a focus on quality and efficient design workflows.

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