Senior Physical Design Engineer

Overview

In this role you will drive the physical implementation of complex satellite SoCs, working within a multinational team to deliver timing-accurate, power-aware designs. You’ll own block-level timing closure, contribute to robust DFT solutions, and collaborate with IP suppliers and external partners to integrate custom and third-party IP. The position blends cutting-edge process technologies with radiation-hardened modem applications, offering impact at the hardware level of space systems. You will partner across design teams to scalable, high-quality silicon.

Responsibilities

• Deliver physical implementation of complex SoCs, including integration of custom designs and third-party IP
• Own block-level timing closure and manufacturing sign-off, including power planning and analysis
• Develop timing constraints with RTL/Logic Design teams at block and chip level
• Implement DFT structures and support chip-level integration, simulation and verification
• Improve design scripts and tool flows
• Collaborate with design teams, IP suppliers, EDA vendors and external design service providers

Key requirements

• 8+ years of experience as a Physical Design Engineer
• Bachelor’s degree in Electrical Engineering, Computer Science or related field
• Experience with ASIC/COT physical design flow (synthesis, floor-planning, P&R, CTS, parasitic extraction, STA, timing closure, physical verification, power analysis, formal verification, DFT/DFM and ATPG)
• Experience with deep sub-micron technologies (28nm or below)
• Experience with Cadence or Synopsys EDA tool flows
• Strong scripting skills (Tcl, Python, Perl or similar)
• Strong analytical and problem-solving abilities
• Experience working with cross-functional design teams, third-party IP suppliers and external design partners

• cross-functional collaboration
• analytical thinking
• problem-solving
• ASIC/COT physical design flow
• timing closure
• power analysis

…