Overview
In this senior, hands‑on leadership role you will steer a digital design team across complex ASIC/FPGA projects. You will stay involved in RTL design while guiding architectural decisions, optimization, and delivery to meet performance and schedule targets. You’ll shape engineering processes and collaborate across architecture, software and verification to drive high‑impact hardware development. This position offers influence over technical direction, tool choices, and future product development within a growing organization.
Responsibilities
- Lead and develop a team of digital design engineers
- Provide technical leadership on complex ASIC and FPGA projects
- Remain hands-on with RTL design and inform architectural/implementation decisions
- Own project delivery, ensuring performance, quality, and schedule adherence
- Drive optimisations in timing, power, area and throughput
- Collaborate with architecture, verification, software and other disciplines
- Shape design methodologies, processes and engineering best practices
- Translate product requirements into clear hardware objectives
- Support technical discussions with customers and senior stakeholders
- Identify opportunities to improve development efficiency via new tools/methodologies
Key requirements
- Strong commercial RTL design experience using Verilog and/or SystemVerilog
- Previous line management or people management experience
- Experience leading technical projects and coordinating engineers
- Experience with industry-standard simulation and synthesis tools
- Ability to balance hands-on technical work with leadership and team development
- Strong communication skills with engineers and senior stakeholders
- leadership
- mentoring
- cross-functional collaboration
- RTL design (Verilog/SystemVerilog)
- ASIC/FPGA development
- simulation tools
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