Digital Design Engineer (AP)

Company: Cirrus Logic
Apply for the Digital Design Engineer (AP)
Location: Edinburgh
Job Description:

Overview

As a Digital IC Design Engineer at Cirrus Logic, you will contribute to the development of high-performance digital IP and SOCs for consumer mobile markets. You will work within a cross-functional team in Edinburgh to design digital architectures, write RTL, and verify blocks, shaping next-generation mixed-signal solutions. You’ll mentor junior engineers and influence group growth while upholding IP quality and engineering reviews. This hybrid role blends hands-on design with collaboration across disciplines, offering growth and impact in a culture that values inclusion and practical innovation. You’ll join a mission-driven, technically rigorous environment at the forefront of mixed-signal R

Pay / Benefits

  • hybrid work model
  • career development opportunities
  • inclusive culture
  • collaborative environment
  • competitive compensation
  • stock/benefits not specified

Responsibilities

  • Collaborate with a team to deliver complex mixed-signal products and IPs
  • Design and develop new digital circuit architectures on advanced process nodes and develop block-level testbenches
  • Contribute to technical reviews and ensure IP quality using checklists
  • Mentor and supervise junior engineers and support team growth

Key requirements

  • Bachelor’s in Electrical Engineering (or equivalent) with proven digital CMOS circuit design background
  • Experience implementing complex digital circuits/sub-systems in RTL (Verilog/SystemVerilog)
  • Understanding of digital system-level design, bus protocols, clock/reset architectures
  • Verification of block-level digital designs and knowledge of synthesis and timing analysis
  • Experience with Linting, CDC, RDC tools
  • Strong interpersonal, organizational, and communication skills
  • Self-motivated with analytical and problem-solving abilities
  • Ability to work in a dynamic, urgent environment
  • collaboration
  • communication
  • problem-solving
  • Verilog/SystemVerilog RTL design
  • digital CMOS design
  • bus protocols and chip-level clock/reset architectures

Posted: September 14th, 2026