Senior IC Layout Engineer – Cambridge

Overview

As a Senior IC Layout Engineer, you will own custom analog layout and verification for multi-Gigabit SerDes and memory IO in advanced nodes. You’ll lead layout activities within a growing semiconductor team, shaping final products and enabling career progression. The role combines hands-on analog layout with high-speed circuit challenges, driving layout quality, parasitic minimisation, and robust power/ESD practices. This is a hybrid role based in Cambridge with opportunities to impact on next-generation designs.

Pay / Benefits

• competitive salary
• pension
• private medical
• visa sponsorship
• relocation assistance

Responsibilities

• own custom analog layout and verification of circuits, blocks, and IP for multi-Gigabit SerDes and memory IO
• lead chip layout activities and coordinate with cross-functional teams
• design high-speed or high-frequency circuits (amplifiers, PLLs, DLLs, buffers, regulators, filters, data converters)
• apply layout techniques to meet matching constraints, minimise parasitics, and ensure power grid and ESD compliance

Key requirements

• experienced analog IC layout engineer with background in high-speed designs
• proven in custom analog layout for high-speed transceivers or similar circuits
• familiar with modern nodes (28nm, 14/16nm, 7nm)
• proficient with EDA tools: Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, including parasitics extraction, EM, IR drop, and ESD modeling

• leadership
• cross-functional collaboration
• effective communication
• Cadence Virtuoso
• Spectre/HSpice
• Calibre/PVS

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