Senior Digital Design Engineer

Company: Analog Devices
Apply for the Senior Digital Design Engineer
Location: Edinburgh
Job Description:

Overview

As a Senior Digital Design Engineer in the Data Center & Energy group in Limerick, you will shape RTL for high-reliability mixed-signal SoCs powering data centers and energy infrastructure. You’ll work with cross-functional teams to deliver robust digital content integrated with analog and firmware. You’ll own RTL development, verification, and timing closure, contributing to scalable, manufacturable solutions. The role combines hands-on design with collaboration and optimization in a fast-paced, agile environment. This position offers growth through multidisciplinary challenges and impact on critical energy and data-center technologies.

Responsibilities

  • Develop and verify RTL for digital blocks and subsystems with functional correctness and timing closure
  • Perform synthesis, static timing analysis, and support DFT insertion and pattern generation
  • Collaborate with analog, firmware, and validation teams to integrate digital content into mixed-signal SoCs
  • Assist with silicon bring-up and debug; support lab measurements and correlation to simulation
  • Contribute to methodology improvements and automation initiatives

Key requirements

  • BS in Electrical or Computer Engineering
  • 4+ years of experience in ASIC/SoC digital design
  • Proficiency in Verilog/SystemVerilog and scripting languages (Python, C)
  • Familiarity with RTL-to-GDS flows (e.g., Genus, Innovus, Tempus, Conformal)
  • Understanding of DFT concepts and basic test strategies
  • Working knowledge of analog circuit operation and lab practices
  • Strong problem-solving skills and ability to work independently with minimal supervision
  • Good organization; written and verbal communication skills
  • strong problem-solving
  • independence and self-management
  • clear written and verbal communication
  • Verilog/SystemVerilog
  • Python, C
  • RTL-to-GDS flows (Genus, Innovus, Tempus, Conformal)

Posted: September 17th, 2026