Senior SoC Subsystem Design Architect

Arm Solution Engineering’s Front End design team in Cambridge is seeking an experienced RTL design engineer to contribute to subsystem designs for GPU and other IP. You will develop RTL, SDC/UPF constraints, integrate IPs and work with verification and implementation teams to ensure high‑quality designs.

The role requires SystemVerilog/Verilog HDL skills, strong RTL design grounding, UNIX scripting, and collaboration across CPU, GPU, multimedia IP.

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