Lead FPGA RTL Engineer for High-Speed Trading | Hybrid

Ecm Selection in Cambridge’s R&D office is seeking a senior FPGA engineer to lead the end-to-end FPGA systems design, focusing on high-speed RTL logic for nanoseconds-scale trading. You’ll collaborate closely with software engineers writing in Rust and C++ to deliver robust solutions.

The role offers hybrid working and a friendly, senior team environment in north Cambridge, with parking and flexible hours. Remuneration is tailored to experience.

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