Design Verification (DV) Engineer

Overview

In this role you will design and maintain verification environments for FPGA/ASIC hardware, enabling high-speed, low-latency trading systems. You will work closely with hardware designers to troubleshoot RTL and bring up new projects in a hybrid open-source/proprietary tooling ecosystem. You will contribute to both open-source and internal tooling, advancing verification maturity across our hardware platforms. This role offers a technically challenging, fast-paced environment at the frontier of trading hardware.

Pay / Benefits

• discretionary performance-based bonuses
• competitive benefits package
• salary commensurate with experience

Responsibilities

• Create testbenches and tests for the hardware platform in a flexible verification environment
• Write detailed verification plans
• Root-cause RTL bugs quickly and efficiently
• Collaborate with designers for rapid bring-up and debugging
• Manage test suites and CI infrastructure
• Develop and improve open-source and internal verification tools

Key requirements

• 2+ years of RTL functional verification experience for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Proficiency in SystemVerilog and UVM
• Proficiency in Python
• Linux environment familiarity
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience a plus
• Bachelor in Computer Science, Electrical Engineering, or related field

• superb debugging and analytical skills
• strong collaboration with designers
• ability to quickly diagnose issues under pressure
• SystemVerilog
• UVM
• Python

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