Senior RTL Design Engineer – CPU Frontend

Overview

In this role you will architect and implement new RISC-V core features using Chisel, drive performance and power optimizations, and integrate work into SiFive’s Chisel/FIRRTL framework. You will verify designs, collaborate with verification and physical implementation teams, and shape microarchitecture while sharing knowledge through strong documentation. This position offers impact across high-performance compute platforms and a culture of collaborative design. A strong hook is the opportunity to advance RISC-V implementations at scale.

Pay / Benefits

• comprehensive benefits package
• healthcare
• retirement plans
• paid time off
• potential equity or incentive compensation

Responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel
• Integrate content into Chisel/FIRRTL framework and improve automation for documentation, tests, and packaged software
• Perform initial sandbox verification and collaborate on thorough verification test plans
• Collaborate with physical implementation team to meet frequency, area, and power goals
• Work with performance modeling team for exploration and optimization to achieve performance targets
• Microarchitecture development and specification; document and contribute to a collaborative design culture

Key requirements

• BS/MS in computer science, computer engineering, electrical engineering or related field, or equivalent experience
• 3+ years design experience
• Experience with CPU RTL design in instruction fetch, decode, branch prediction, coherent caches, cache prefetching, TLBs
• Proficiency in Verilog, SystemVerilog, or VHDL

• Attention to detail
• Teamwork / collaboration
• Strong communication
• Verilog/SystemVerilog/VHDL
• Chisel/Scala (Nice-to-have)
• Bluespec or other HDLs (Nice-to-have)

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