Overview
In this role you will contribute to designing and integrating IPs into complex subsystems and SoCs for a range of applications. You’ll work with cross‑functional teams to define microarchitecture, RTL, and verification plans, while optimizing power and performance. You’ll engage in system-level trade‑offs and debugging to help deliver scalable hardware across IoT, Automotive, and Infrastructure domains. This position offers global collaboration and exposure to advanced ARM architectures, with a strong focus on impact and hands-on design delivery.
Pay / Benefits
- hybrid working patterns
- accommodations available during recruitment
- equal opportunities employer
Responsibilities
- Understand incoming IPs and interfaces, and work with subsystem/SoC components
- Develop subsystem microarchitecture specifications and RTL
- Review verification plans and assist debugging and issue resolution
- Collaborate with performance analysis to improve system performance
- Propose refinements to IP teams based on integration insights
- Execute design checks, fix bugs, and support design methodologies
- Balance multiple tasks with project management to plan schedules
- Guide and support team members to enable project completion
Key requirements
- Bachelor or Master in Electrical/Computer Engineering or related field
- Experience with digital hardware design and Verilog HDL
- Understanding of complex SoC design techniques
- Experience with static design checks (CDC, RDC, X-prop, lint)
- Experience creating design specifications
- Scripting in Perl, Python or similar
- Strong RTL subsystem delivery track record
- Ability to perform high-level PPA trade-offs and justify choices
- Experience with synthesis, timing analysis, and power management techniques
- Good communication and collaboration skills
- communication
- collaboration
- problem-solving
- Verilog HDL
- SystemVerilog
- synthesis
…
