Staff Design Engineer

Overview

As a Staff Subsystem Design Engineer, you will help shape subsystem architectures and IP for Edge, Physical, and Cloud AI solutions. You’ll collaborate with architecture, verification, and implementation teams to deliver robust, power- and area-efficient designs. You’ll translate high-level requirements into microarchitectures, develop RTL and integrate mixed IP into cohesive subsystems. You’ll drive design quality and trade-off discussions to meet performance targets and timelines. This role offers the chance to influence next‑generation AI hardware within a global, innovative team.

Pay / Benefits

• hybrid working
• accommodations during recruitment
• equal opportunity employer
• diverse global team
• opportunity to shape next‑gen AI hardware
• global collaboration across Arm teams

Responsibilities

• Analyse architectural and system specifications with architects to refine solutions
• Develop subsystem and IP microarchitecture specifications from high-level requirements
• Design new IP and subsystem logic and integrate Arm and third-party IP into subsystems
• Understand IP functionality, interfaces and system-level interactions for robust integration
• Develop and maintain design intent, including UPF and timing constraints
• Perform design checks (Lint, CDC, RDC, X-propagation) and other static checks
• Articulate design decisions considering performance, power, area, timing and complexity trade-offs
• Collaborate with verification teams to review test plans and support debugging complex designs
• Work with implementation, performance and power teams to meet requirements
• Improve design methodologies and flows and drive timely delivery
• Provide technical guidance and reviews to other engineers as part of the team

Key requirements

• Bachelor’s, Master’s or PhD in Electrical/Electronics/Computer Engineering or related discipline
• 10+ years of relevant industry experience
• Extensive hands-on digital RTL design and microarchitecture development using SystemVerilog/Verilog
• Strong track record of delivering sophisticated IP or RTL subsystem designs
• Deep understanding of RTL design techniques for complex subsystems/SoCs
• Ability to translate high-level specs into efficient microarchitectures
• Familiarity with industry-standard EDA tools and methodologies
• Experience with static design checks (Lint, CDC, RDC, X-propagation)
• Experience with synthesis, timing analysis and power-management techniques
• Understanding of low-power design methodologies (UPF, clock/power gating, multi-domain)
• Ability to trade-off performance, power, area, timing and complexity with clear rationale
• Knowledge of on-chip protocols/interfaces (AMBA AXI, APB, streaming)
• Strong computer architecture knowledge and processor-based systems
• Ability to work cross-functionally and communicate effectively
• Self-driven and motivated with ownership mindset
• Knowledge of AI-powered software development tools and scripting workflows (e.g., Codex, Copilot)
• Excellent communication, collaboration and teamwork skills

• collaboration
• communication
• ownership
• SystemVerilog/Verilog
• RTL design
• microarchitecture

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