Senior DTCO DRAM Periphery Circuit Designer / Architect

Overview

As Senior DTCO DRAM Periphery Circuit Architect, you will lead design and exploration of advanced DRAM periphery circuits within imec’s memory initiatives. You’ll bridge transistor-level design with array organization and macro architecture to enable robust, high-performance DRAM solutions. You’ll own key peripheral blocks and contribute to tape-out readiness across layout-aware design, verification, and system integration. This role offers deep exposure to memory roadmap definition and cross-functional collaboration. You will shape future memory concepts while working in an inclusive, multidisciplinary environment with strong technical ownership.

Pay / Benefits

• market-competitive salary
• fringe benefits
• inclusive, multicultural environment
• opportunity for growth and development via imec.academy

Responsibilities

• Design, analyze and optimize DRAM peripheral building blocks (row/column path circuitry, wordline drivers, sense-amplifier functions, write-path circuits)
• Study interactions between DRAM array, hierarchy, and external protocol; understand DRAM access flow and timing
• Lead from specification through circuit design, simulation, verification and implementation readiness
• Contribute to architectural decisions at subarray, bank and macro levels balancing performance, power, area, robustness
• Collaborate across circuit design, devices, process integration, and system-facing research to enable tape-out and demonstrator/test-chip activities
• Engage in silicon bring-up, debugging, and hardware validation efforts as needed
• Translate architecture/protocol requirements into transistor-level solutions with layout-conscious design

Key requirements

• Master’s degree or PhD in Electrical Engineering, Electronics, or related field
• 6+ years in DRAM industry focused on periphery circuit design
• Deep understanding of DRAM array organization and interaction with periphery and protocol
• Hands-on experience designing and analyzing DRAM peripheral circuits and related submodules
• Familiarity with Virtuoso IC design, Hspice, and Calibre DRC/LVS
• Experience working in multidisciplinary teams and effective cross-domain communication
• Ability to translate requirements into transistor-level circuit solutions; awareness of layout, parasitics, robustness

• strong cross-functional collaboration
• effective communication across specialists
• problem-solving and analytical thinking
• DRAM peripheral circuit design
• array/ subarray hierarchy understanding
• sense-amplifier and timing control expertise

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