Senior Design Verification Engineer – Cryptography

Overview

In this role you will lead and execute verification for cryptographic IP and subsystems, shaping verification strategies in a collaborative, high-trust environment. You will extend UVM testbenches, develop Python automation, and apply formal methods to ensure robust, secure designs. You’ll influence verification approaches, mentor peers, and drive coverage and sign-off quality in a fast-growing, mission-driven company. This is a remote opportunity for a UK-based engineer who thrives in small teams and values high-quality verification for security-critical systems.

Pay / Benefits

• Competitive base salary
• share options
• fully remote role (UK-based)
• visa sponsorship available
• opportunity to build from the ground up
• collaborative, small-team culture

Responsibilities

• Build and extend UVM testbenches for cryptographic IP/subsystems
• Develop Python-based verification tools and automation
• Apply formal verification techniques creatively
• Define verification methodologies, plans, and coverage models
• Architect testbenches using UVM and formal approaches
• Lead verification for IPs/subsystems: estimation, scheduling, task allocation, progress reporting
• Drive coverage closure and sign-off quality
• Mentor junior engineers and raise team capability

Key requirements

• Strong UVM-based verification experience at IP and subsystem levels
• Proven ability to build UVM testbenches from scratch
• Proficiency in Python for verification automation
• Solid experience with SystemVerilog Assertions (SVA)
• Minimum 4 years of experience

• Collaborative mindset
• Clear communication
• Mentoring and leadership
• UVM
• Python
• SystemVerilog

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