Senior Physical Design Engineer

Overview

Senior Physical Design Engineer in Edinburgh, responsible for RTL-to-GDS2 implementation of complex ASICs. You’ll collaborate with Digital, Analog, and DFT teams to ensure on-time, high-quality results while shaping P&R methodologies. The role blends independent work with teamwork within Cirrus Logic’s innovative hardware culture, offering exposure to cutting-edge mixed-signal SOCs. This is a hybrid position, focused on delivering reliable tapeouts and performance in consumer markets.

Pay / Benefits

• hybrid work model

Responsibilities

• RTL-to-GDS2 physical implementation for complex ASICs
• Collaborate with Digital Design, Analogue Layout and DFT teams
• Participate in project scoping and planning
• Develop P&R methodologies for continuous improvement

Key requirements

• Bachelor’s in Electrical Engineering or related field (or higher)
• Proven experience in Physical Design
• Hands-on experience with EDA tools: Design Compiler, Primetime, Innovus, Voltus, Conformal
• Experience in RTL synthesis, timing constraints, floorplanning, power planning, clock tree synthesis
• P&R optimization, timing closure, ECO implementation
• Static timing analysis and Logical Equivalence Checks
• Power and EMIR analysis
• Full design flow to tapeout with scripting for automation
• Strong debugging/analysis skills and good communication

• Good communication
• Excellent collaboration skills
• Synopsys Design Compiler
• Primetime
• Cadence Innovus
• Voltus

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