Senior FPGA Engineer

Overview

As a Senior FPGA Engineer you will design RTL for FPGA and ASIC platforms to enable next-generation communication systems. You will work within an engineering team to deliver reliable digital hardware for high-performance applications. The role focuses on RTL development using Verilog or SystemVerilog, contributing to system-level signal processing and digital communications. You will collaborate with cross-functional teams and adapt to evolving requirements, with relocation support available. This is a hands-on, impact-driven opportunity to shape scalable hardware solutions in Cambridge.

Pay / Benefits

• relocation assistance
• excellent benefits package

Responsibilities

• RTL design and verification for FPGA and ASIC development
• Develop and maintain Verilog/SystemVerilog code for digital hardware
• Collaborate with signal processing and communications teams on interface and timing requirements
• Contribute to design reviews and unit testing to ensure reliability
• Assist with debugging and optimization of hardware blocks

Key requirements

• In-depth RTL design experience using Verilog or SystemVerilog for ASIC/FPGA
• Knowledge of signal processing or digital communications
• Experience with digital hardware designs in ASIC/FPGA environments
• Experience with Python scripting

• leadership
• collaboration
• problem-solving
• Verilog
• SystemVerilog
• RTL design

…