Senior Subsystem & SoC Design Engineer

Overview

In this role, you will contribute to the specification, design and verification of subsystems and testchips, building RTL and design- intent deliverables for complex SoCs. You will integrate IPs, run design checks, and help refine micro-architecture while collaborating with verification and implementation teams to ensure timely, high-quality delivery. The role sits in Arm’s Solution Engineering frontend design team, shaping GPU and control subsystems for edge, physical and cloud AI applications. You will work in a dynamic, cross-functional environment with a focus on impactful subsystem designs.

Pay / Benefits

• hybrid working
• accommodations available during recruitment process
• equal opportunity employer
• diverse and meritocratic workplace
• global presence
• opportunity to work on AI-focused subsystems

Responsibilities

• Develop RTL and design intent deliverables (SDC, UPF)
• Integrate IPs and perform design checks
• Contribute to micro-architecture specification
• Collaborate with verification to review test plans and with implementation to optimize designs
• Plan work, track progress and report status to ensure timely delivery

Key requirements

• Hands-on SystemVerilog or Verilog RTL design experience
• Solid RTL design understanding for complex SoC development
• Experience with static design checks, power and clock domain crossing, synthesis
• Strong computer architecture knowledge with experience in CPU, GPU, multimedia IP, interconnects, memory controllers and peripherals
• Knowledge of UNIX environment and scripting (Python, Perl, UNIX shell)
• Ability to write specifications and documentation for complex designs

• SystemVerilog or Verilog HDL
• RTL design for SoCs
• SDC
• UPF
• UNIX scripting (Python, Perl)
• C/C++ and/or assembly (nice to have)

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