Principal Analog Design Engineer

Overview

In this Senior Analog Design Engineer role, you design high-performance analog power management circuits at the transistor level to support Allegro’s power management ICs and motor drivers. You will work with cross-functional teams to ensure robust, on-time delivery and to advance core product development. The role combines hands-on design, verification planning, and mentorship within a culture focused on autonomy and technical excellence. You’ll contribute to a mission-driven environment that values innovation and collaboration.

Responsibilities

• Design analog power management circuits (op-amps, comparators, level-shifters, gate drivers, charge pumps) to meet specifications
• Perform worst-case simulations to ensure robust performance across conditions
• Negotiate specifications with Systems Engineers, balancing performance, cost, and development time
• Own block development, create verification plans, support production testing, ensure on-time delivery
• Collaborate with layout, test, and validation teams to understand block impact on chip-level results
• Lead small projects or mentor junior engineers, fostering technical excellence and collaboration

Key requirements

• Bachelor’s or Master’s in Electrical Engineering with 5+ years (or 3+ years with Master) in analog/mixed-signal IC design
• Strong knowledge of CMOS technology and physical design for power management (parasitics, dielectric, junction isolation)
• Proven problem solver with ability to work independently
• Proficiency with Cadence chip design suite and modern simulation environments
• Strong analytical and interpersonal skills to influence and communicate complex concepts

• analytical thinking
• interpersonal effectiveness
• ability to influence others
• Analog/mixed-signal IC design
• CMOS technology and physical design concepts
• Cadence chip design suite

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