NVM Circuit Design Engineer (MH-UK-50021294)

Overview

In this role you will lead Cirrus Logic’s centralized IP Integration Digital team to deliver high-quality Digital IP for mixed-signal chips. You’ll partner with product design leadership to set strategy, define requirements, and ensure on-time execution for in-flight programs. Your leadership will guide characterization, verification, and integration of both 3rd party and custom IP, working across layout, design, and foundry teams. This is a high-visibility opportunity to shape IP flows, improve methodologies, and support mobile and IoT applications at scale.

Responsibilities

• Manage, mentor & grow the IP integration team
• Lead design, simulation, and optimization of Digital IP circuits
• Deliver characterization and modeling of Digital IP and I/O libraries
• Develop and maintain IP and I/O library models and flows
• Collaborate with foundry teams on 3rd party IP development and release
• Coordinate with quality teams to ensure IP qualification and communicate requirements to foundries, vendors, and customers

Key requirements

• 10+ years of proven experience leading engineering teams
• Master’s degree in Electrical Engineering or closely related field
• Strong understanding of transistor-level circuit simulation and design
• Knowledge of power and speed tradeoffs in Digital IPs
• Experience in low leakage IP design for mobile and IoT
• Ability to guide layout engineers
• Proficiency with Cadence schematic capture, layout, and simulation tools
• Effective oral and written communication

• leadership
• cross-functional collaboration
• clear communication
• transistor-level circuit design
• digital IP characterization and modeling
• Verilog models for IP

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