Physical Design Engineer Jobs in Greater Bristol Area, United Kingdom at Platform Recruitment
Title: Physical Design Engineer
Company: Platform Recruitment
Location: Greater Bristol Area, United Kingdom
Senior / Staff Physical Design Engineer
Location: Bristol Area
Salary: Circa £250,000 + Equity
Working Arrangement: On-site
Employment Type: Permanent
I’m recruiting on behalf of a rapidly growing semiconductor company developing next-generation accelerator technology for high-performance AI computing.
They are seeking a Senior or Staff Physical Design Engineer to lead the implementation of digital control logic within a tightly integrated mixed-signal and analogue subsystem. This is an opportunity to solve complex physical-design challenges involving advanced process nodes, high-frequency circuits and custom analogue/RF integration.
The Role
You will take ownership of physical design from architecture through to sign-off, working closely with analogue, digital and DFT engineers.
Key responsibilities will include:
- Architecting and implementing high-performance digital control solutions.
- Floorplanning, placement, routing and timing closure.
- Developing low-power, low-skew clock-distribution networks.
- Designing power grids around complex analogue floorplans.
- Supporting multi-voltage-domain design flows.
- Performing timing analysis across analogue and digital interfaces.
- Achieving DRC, LVS and ERC closure on advanced-node processes.
- Customising and automating physical-design flows using Python and Tcl.
- Supporting DFT implementation and successful tape-out.
Essential Experience
- At least seven years’ experience in ASIC or SoC physical design.
- Strong knowledge of high-frequency, high-performance digital implementation.
- Experience across floorplanning, place and route, CTS, STA and sign-off.
- Proven work with advanced semiconductor process nodes.
- Python and Tcl scripting for EDA flow automation.
- Experience integrating digital logic with analogue, RF or mixed-signal circuitry.
- Strong communication and cross-functional collaboration skills.
Experience with sub-7nm tape-outs, PCIe, SerDes, PHY integration, ESD requirements or customised DFT flows would be highly advantageous.
The successful engineer will receive a circa £250,000 salary, meaningful equity and the opportunity to influence the architecture of a genuinely cutting-edge semiconductor platform.
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