Lead RTL Design Engineer for Photonic Compute Path

TRIA seeks a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for its photonic compute path. You will define the digital architecture, clock/reset strategy and interfaces, and write synthesizable RTL for control state machines and data paths.

Collaborate across photonics, analog, verification and layout teams through tapeout and first-silicon bring-up. 8+ years in ASIC RTL design with SystemVerilog, timing constraints and high-speed interfaces is required.

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