Senior Design Engineer

Overview

In this role you will design and optimize RTL for FPGA and ASIC targets to enable advanced non-terrestrial 5G base stations and satellite-enabled mobile connectivity. You will work within a multidisciplinary team to translate requirements into robust architectures and verify them across the full design lifecycle. You’ll shape high-throughput signal processing hardware and contribute to timing, resource and power optimizations. This is a chance to impact next-generation communications in a cutting-edge, space-enabled environment.

Responsibilities

• Develop RTL for FPGA/ASIC targets
• Translate system/algorithm requirements into micro-architectures
• Create testbenches and verify designs on FPGA platforms
• Optimize timing, throughput, hardware resources and power
• Oversee the full design lifecycle from micro-architecture to physical implementation
• Collaborate with Algorithm, System Architecture and Verification engineers
• Produce design specifications and technical documentation

Key requirements

• Expert-level Verilog / SystemVerilog
• Strong FPGA and/or ASIC design experience
• Experience with synthesis and timing analysis
• Knowledge of high-throughput data or signal-processing designs
• Experience optimizing timing and hardware resources
• Strong knowledge of industry-standard EDA simulation and synthesis tools
• Experience delivering complex, integrated digital designs
• Advantageous: 5G, DSP algorithms, UVM, AMBA, SystemC/C++, PCIe, JESD, Python, AMD/Xilinx FPGA technology

• Collaborative mindset
• Clear technical communication
• Problem-solving under complex constraints
• Verilog/SystemVerilog
• FPGA/ASIC design
• Synthesis and timing analysis

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