Senior Subsystem Design Engineer — RTL/IP Expert

Arm Limited in Cambridge is seeking a Staff Subsystem Design Engineer to lead RTL and subsystem IP design for next-generation compute platforms. You will specify, microarchitect and integrate complex IP and subsystems, collaborating with architecture, verification, and implementation teams to ensure high-quality, power-efficient designs.

The role requires 10+ years in RTL design, strong SystemVerilog/Verilog skills, and experience with AMBA AXI/APB interfaces, SVA and UVM are advantageous.

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