SOC Architect – R & D

Overview

In this role you will drive the integrated chip architecture for a high‑stakes, cutting‑edge quantum computing environment. You will shape the overall system design, working as a key technical contributor within a cross‑functional team. You’ll coordinate with suppliers, the fab, and packaging houses to ensure precise definitions as you balance new technology with traditional ASIC/SOC processes. Your R&D background and track record of tape‑outs will underpin decisions on advanced nodes and heterogeneous integration, delivering a scalable, multi‑technology SOC. This is a senior, strategic opportunity with meaningful impact on product architecture and ecosystem collaboration.

Pay / Benefits

• visa sponsorship
• relocation support

Responsibilities

• Define and own the SOC/ASIC architecture for multi‑technology integration
• Lead cross‑functional architecture decisions across design, physics, and packaging
• Manage relationships with suppliers, fab, and custom packaging houses
• Oversee chiplet partitioning, 2.5D/3D packaging and SiP strategies
• Evaluate and select advanced processes and technology nodes for new products
• Coordinate integration of PICs, photonics, GaN, SiGe with conventional silicon processes
• Support new product assessments and drive architectural trade‑offs
• Drive architecture alignment with product goals and manufacturing constraints

Key requirements

• Significant years of experience in ASIC/SOC hardware architecture engineering
• Proven track record of multiple tape‑outs
• Experience in R&D environment
• Familiarity with new/advanced node processes and nm technology
• Experience with heterogeneous integration and packaging strategies (2.5D/3D, chiplets, partitioning)
• Knowledge of PICs, photonics, GaN, SiGe, FinFET, FD‑SOI
• Ability to manage relationships with suppliers, foundries, and packaging houses
• Visa sponsorship and relocation support available for qualified candidates

• Stakeholder management
• Strategic thinking
• Cross‑functional collaboration
• ASIC/SOC architecture
• System integration of multiple technologies
• Tape‑outs and design for manufacturing

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